HERON-FPGA IP by Function

We have many examples for our HERON modules that have FPGA. These examples can be used to learn how to use specific parts of the modules, or can be used as a starting point for your development. Some of the examples could even be useful in your system without making any changes.

Camera Link Interface.
For : HERON-FPGA3, HERON-FPGA4, HERON-FPGA5, HERON-FPGA7, HERON-FPGA9, HERON-FPGA12, HERON-FPGA14
Camera Link is a standard interface used by many camera manufacturers. It uses a standard set of signals for a variety of camera types and sizes. This VHDL allows you to connect any Camera Link camera to one of the modules, and to receive the image data in your FPGA. There are a number of VHDL blocks included that can perform common functions like auto-detection of the Image size, Selection of a Region of Interest to use etc etc.
The IP is used as it is in the FPGA imaging demo. You can use it as it is, or as a basis for your own FPGA imaging design, possibly taking advantage of our Image Processing VHDL modules too. 
The examples we supply use an 8 bit monochrome area scan camera connected using Camera Link Base configuration. All other configurations are supported by the Camera Link interface that we provide but if you need the examples to work with a different configuration you will need the changes to support the exact configuration you need. See the Camera Link page for more information.

Transient Analysis and Pattern generation.
For : HERON-IO2, HERON-IO5
These modules have a combination of A/D and D/A interfaces. They are much faster than the data rate that can be handled by a C6000 module or a host computer. One way to use the full speed of the D/A interfaces is to use the FPGA to store a pattern that is output on the D/As repeatedly - Pattern Generation. One way to use the full speed of the A/D interfaces is to capture a burst of data at the full rate, storing it in the FPGA, and to output it at a lower rate afterwards - Transient Analysis.
This is what these examples do, and they come with programs for the Host PC and C6000 modules to demonstrate them.

Data Streaming.
For : HERON-IO2, HERON-IO5
These modules have a combination of A/D and D/A interfaces. They are much faster than the data rate that can be handled by a C6000 module or a host computer. One way to use them is to clock them at lower than the full rate, so that data can be streamed into and out of the processor.
This is what these examples do, and they come with programs for the Host PC and C6000 modules to demonstrate them.

Digital I/O and RS232.
For : HERON-FPGA3, HERON-FPGA4
These modules have some general purpose digital I/O connectors. Often these connectors are used for LVTTL (3.3V) inputs and outputs. These examples offer a range of inputs and outputs that can be set and read over the HERON FIFOs. They also implement an RS232 connection controlled via the Heron serial Bus. 
These examples allow users to use an FPGA module as a general purpose Digital I/O module without changing the FPGA program. Alternatively the projects can be used as a starting point for your own FPGA application that includes digital I/O.

SDRAM based FIFOs.
For : HERON-FPGA5, HERON-FPGA7, HERON-FPGA9, HERON-FPGA12, HERON-FPGA14
These modules have some SDRAM connected to and controlled by the FPGA. The Hardware Interface Layer performs the function of the SDRAM controller, and offers a VHDL interface to your own design. This example shows how you can use that SDRAM with the H.I.L. interface to create one or a pair of large FIFOs (depending on the number of memory banks on the module) connected between a HERON input FIFO and a HERON output FIFO.
As well as demonstrating how to use the HIL, this example can be used as it is to provide large buffers in a HEART data stream. This could be useful for example when connecting a fast device (A/D etc) to a Host PC as it will help to cope with the bursty nature of the PCI interface.

SDRAM memory test.
For : HERON-FPGA5, HERON-FPGA7, HERON-FPGA9, HERON-FPGA12, HERON-FPGA14
These modules have some SDRAM connected to and controlled by the FPGA. Hardware Interface Layer performs the function of the SDRAM controller, and offers a VHDL interface to your own design. This example performs a memory test on the entire SDRAM buffer. 
As well as demonstrating how to use the HIL, this example can be used to test your hardware - giving you confidence that it is still operating correctly.

Getting Started with the Embedded PowerPC on a HERON-FPGA module that has a Virtex-II Pro or Virtex-4 FX Device
For: HERON-FPGA9, HERON-FPGA12
These modules have an FPGA with a PowerPC 405 processor embedded in it. The Xilinx EDK is the development environment for PowerPC programs. This example  C file makes the LEDs on the HERON module flash. The C code uses a pointer to an address where the hardware is expected to have implemented a register from where the LEDs are accessed. This demonstrates how to use the Xilinx EDK and its debug tools.

Connecting the PowerPC processor to Hardware
For: HERON-FPGA9, HERON-FPGA12
This example looks at how the PowerPC and FPGA on a module that has a VirteX-II Pro or Virtex-4 FX can be used together in a way that makes best use of the power of each element. This project provides an example that combines the PowerPC and FPGA by implementing a CoreGen FFT component in the FPGA. The PowerPC feeds the FFT component with data and also controls and monitors the operation of that logic. This framework can be used to implement many other different types of FPGA function block that can be connected to the PowerPC. 

Connecting the PowerPC processor to DDR SDRAM
For: HERON-FPGA9, HERON-FPGA12
This example looks at how to connect the PowerPC on a module that has a Virtex-II Pro or Virtex-4 FX device to the DDR memory interface of the FPGA. The project provides a demonstration of the PowerPC accessing one half of a bank of memory while the FPGA gates access the other half.

RS232.
For : all
There is a general example that discusses how to implement an RS232 UART in your FPGA design. Most modules have protocol converter chips that convert the signals from your UART into the correct signals for connecting to an RS232 device. 

Front Panel Data Port (FPDP).
For :HERON-FPGA3, HERON-FPGA4, HERON-FPGA5, HERON-FPGA7, HERON-FPGA9, HERON-FPGA12
There is a general example that shows how you can connect the FPDP interface to a HERON FPGA module using the general purpose Digital I/Os.
This can be used to connect an FPDP peripheral to your HERON system.

Heron Serial Bus (HSB) mastering.
For : all
There is a general example of how you can use the H.I.L. to perform bus mastering of the HSB from your FPGA design.
This can be used to send control data between modules, or even to configure your HEART connection - particularly useful in an embedded system.

Fast Fourier Transform (FFT).
For : all
There is an example of how to use the Xilinx Core generator FFT block in a HERON module with FPGA. There is also a development framework that goes with this example.

Digital down Converter (DDC).
For : all
There is an example of how to use Xilinx Core generator blocks to design a DDC for a HERON module with FPGA. There is also a development framework that goes with this example.

You can download the files for each module type here.

Module Type
Generic examples, RS232, FPDP, HSB mastering, FFT, DDC, Camera Link etc	All FPGA generic examples  8,041 Kbytes
HERON-FPGA3	All examples and IP for HERON-FPGA3  2,888 Kbytes
HERON-FPGA4	All examples and IP for HERON-FPGA4  3,504 Kbytes
HERON-FPGA5	All examples and IP for HERON-FPGA5    2,071 Kbytes
HERON-FPGA7	All examples and IP for HERON-FPGA7   3,718 Kbytes
HERON-FPGA9	All examples and IP for HERON-FPGA9    3,946 Kbytes
HERON-FPGA12	All examples and IP for HERON-FPGA12    3,946 Kbytes
HERON-FPGA14	All examples and IP for HERON-FPGA14    1,911 Kbytes
HERON-IO2V	All examples and IP for HERON-IO2V2  3,449 Kbytes
HERON-IO5/HERON-IO5-DO	All examples and IP for HERON-IO5  2,330 Kbytes

There are also a number of useful application notes which are listed and downloadable from the application notes page.

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