Connecting the PowerPC Processor to DDR SDRAM

The HERON-FPGA9 has a  Virtex^®-II Pro device which consists of an FPGA with a PowerPC 405 processor embedded in it. It also has two banks of external DDR SDRAM memory which is available for use by both the FPGA gates and directly by the PowerPC core. This example looks at how to connect the PowerPC  to the DDR memory interface of the FPGA. An example project is provided that demonstrates the PowerPC^® accessing one half of a bank of memory while the FPGA gates access the other half.

 

HERON-FPGA9 User Manual

Print friendly version of HERON-FPGA9 Datasheet

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